Electronic systems and devices such as, but not limited to computer systems, mobile devices and phones, set top boxes, printers, etc. are known to include two or more integrated circuits. An integrated circuit as used may refer to a single integrated circuit or a collection of integrated circuits or integrated circuits. Each integrated circuit may include “logic.” Logic and derivatives of the term logic may include any number of integrated circuit components such as, but not limited to, the transistor. As is known in the art, integrated circuit components, such as transistors, may form logic that is capable of performing a variety of operations. Because an integrated circuit may consist of multiple integrated circuits, as used in this disclosure, references herein to logic may physically bridge or span over one or more integrated circuits or integrated circuit packages. Integrated circuits are known to communication with each other using a variety of signals. As used throughout this disclosure, the term “signal” and all derivatives thereof refer to any suitable analog or digital signal carrying information and/or data. The term signal and its derivatives may also refer to one or more voltage levels as is known in the art. For purposes of clarity, the statements made above are applicable throughout this disclosure.
The integrated circuits have core logic which is responsible for performing a particular function. The functions may be programmable or non-programmable. The integrated circuits also have communication buffer logic to communicate with other integrated circuits. The buffer logic minimally includes transmitter logic to transmit outgoing communication signals (e.g., output signals based on a core logic output signal) and/or receiver logic to receive incoming communication signals (e.g., input signals to core logic from another source such as another integrated circuit). This architecture is necessary because the core logic is generally powered using a small voltage source (also known as “a voltage supply” or as “a voltage rail”) while communication signals between integrated circuits generally require logic one values that are larger than the voltage source of the core logic. For example, core logic of an integrated circuit may be powered by a 1.2 V or 1.8 V voltage source while communication signals may have a logic one value of 3.3 or 5.0 V. Accordingly, it is known to use a separate voltage source for the communication buffer logic. The use of one or more power sources in an integrated circuit results in different power domains or voltage islands within the integrated circuit.
This architecture is generally applicable to a wide variety of integrated circuits. For example, processor IC's, memory IC's, chip set IC's and ASIC's all incorporate the core logic/communication buffer logic scheme described above. A processor IC may include any suitable processing integrated circuit or integrated circuit package such as, but not limited to, a central processing unit, a graphics processing unit, processing cores within a processor, processing engines, accelerators, etc. A memory IC may include any integrated circuit or integrated circuit package capable of storing data whether volatile or non-volatile such as, for example, a DRAM. A chip set IC may include any suitable bridge integrated circuit or bridge integrated circuit package such as, but not limited to a northbridge, a southbridge and a combined northbridge+southbridge.
It is further known that electronic devices are consistently being driven to operate faster and consume less power. One way to meet these demands is to supply integrated circuits with faster clocks and smaller voltage supply levels while reducing the gate thickness of individual transistors on integrated circuits. Accordingly a variety of different types of transistors have been developed to meet this demand. For example, a first type of transistors (“1X transistors”) is characterized by supporting a 1.8 V power supply and generating a 1.8 V logic one value. 1X transistors are further characterized by being designed based on, among other things, a reliability criterion that indicates how reliable the transistor will be over a period of time when exposed to a variety of voltage differences between any two terminals of the transistor. As used herein, transistors have three terminals: a gate, a first terminal and a second terminal. 1X transistors presently have a reliability criterion indicating that they will provide 10 years of reliable operation if exposed to no more than 1.8 V plus a predetermined tolerance voltage between any two terminals. The predetermined tolerance value may be any suitable percentage or voltage amount. It is not uncommon to see tolerance values expressed as 20%.
Those having ordinary skill in the art will recognize that other types of transistors may exist. For example, transistors supporting a 3.3 V power supply and generating a 3.3 V logic one value are referred to as 2X transistors. 2X transistors presently have a reliability criterion indicating that they will provide 10 years of reliable operation if exposed to no more than 3.3 V plus a predetermined tolerance voltage between any two terminals. The predetermined tolerance value may be the same as that described above with respect to 1X transistors. Similarly, transistors supporting a 5.0 V power supply and generating a 5.0 V logic one value are referred to as 3X transistors. 3X transistors presently have a reliability criterion indicating that they will provide 10 years of reliable operation if exposed to no more than 5.0 V plus a predetermined tolerance voltage between any two terminals. The predetermined tolerance value may be the same as that described above with respect to 1X transistors.
Although 1X, 2X and 3X transistors were described above with reference to 1.8 V, 3.3 V and 5.0 V respectively, it is understood that 1X, 2X and 3X transistors may be described with reference to another suitable voltage level. For example, a 1X transistor may refer to a transistor that supports a 1.2 V power supply and that generates a 1.2 V logic one value with a similar 10 year reliability criterion if exposed to no more than 1.2 V plus a predetermined tolerance range of approximately 20% between any two terminals.
Because certain transistors can only withstand a predetermined amount of voltage difference between any two terminals, engineers and circuit designers have often used more than one voltage source to supply power to an integrated circuit or to a given power domain or voltage island within an integrated circuit. A prior art example is illustrated in the schematic circuit diagram of an integrated circuit 100 of FIG. 1. More specifically, the integrated circuit 100 of FIG. 1 illustrates one example of prior art communication buffer logic 102. Communication buffer logic 102 is illustrated as including: transmitter logic 104 and pre-buffer logic 106 where the transmitter logic 104 is capable of generating an outgoing communication signal 128. Although not illustrated, one having ordinary skill in the art will recognize that communication buffer logic 102 may include receiver logic that is capable of receiving incoming communication signals from any other suitable source (e.g., from another integrated circuit). In other embodiments, pre-buffer logic 106 (or just voltage range translation logic 112) may be part of the core logic (not illustrated). The pre-buffer logic 106 and the transmitter logic 104 are illustrated as being coupled to two voltage sources: a first voltage source (VDD_1) 108 operating at, for example, 3.3. V and a second voltage source (VDD_2) 110 operating at, for example, 1.8 V. It is understood that other voltage sources may supply power to the remainder of the integrated circuit. For example, core logic may have a third voltage source operating at, for example, 1.2 V.
Pre-buffer logic 106 includes voltage range translator logic 112, a first inverter circuit I1 and a second inverter circuit I2. The voltage range translator logic 112 is coupled to receive at least one core logic output signal 118 from the core logic. The at least one core logic output signal 118 may have a logic one value at any suitable voltage level (e.g., 1.2 V). In one embodiment, the at least one core logic output signal 118 has a logic one value such that the voltage range translator logic 112 may be implemented using 1X transistors. Core logic may be any suitable logic capable of issuing at least one core logic output signal 118 for controlling the output of the transmitter logic 104. As is known, the at least one core logic output signal 118 may include control information and/or transmission information. The control information may enable or disable the transmitter logic 104 and/or receiver logic (not shown). For example, the transmitter logic 104 may be disabled when receiver logic is receiving incoming communication signals. The transmission information may be transmitted in the outgoing communication signal 128 by the transmitter logic 104.
Based on the at least one core logic output signal 118, the voltage range translator logic 112 generates a first translated signal 120 and a second translated signal 122. The first translated signal 120 is input to the first inverter circuit I1 having the first voltage source 108 as its high power supply and having the second voltage source 110 as its low power supply. The second translated signal 122 is input to the second inverter circuit I2 having the second voltage source 110 as its high power supply and having the ground as its low power supply. The first translated signal 120 is characterized as having a voltage range of VDD_2 to VDD_1. That is, a logic zero is represented by a voltage level of VDD_2 while a logic one is represented by a voltage level of VDD_1. The second translated signal 122 is characterized as having a voltage range of 0 V to VDD_2. That is, a logic zero is represented by a zero voltage while a logic one is represented by a voltage level of VDD_2. Accordingly, both of the first and second inverter circuits I1 and I2 may be implemented using 1X transistors.
When the at least one core logic output signal 118 contains transmission information for communication in the outgoing communication signals 128, the first and second translated signals 120 and 122 mirror, match or otherwise mimic the logic states of the transmission information in the at least one core logic output signal 118. However, when the at least one core logic output signal 118 contains control information indicating that transistor logic 104 should be disabled, the first and second translated signals 120 and 122 may take any suitable form to suitable control (and disable) the transmitter logic 104. In the event that the communication buffer logic 106 includes receiver logic (not shown), the pre-buffer logic may supply the first and second pre-buffer logic output control signals 124 and 126 to the receiver logic to enable or disable it based on the control information in the at least one core logic output control signal 118.
The first inverter circuit I1 generates a first pre-buffer logic output control signal 124 based on the first translated signal 120. Similarly, the second inverter circuit I2 generates a second pre-buffer logic output control signal 126 based on the second translated signal 122. Each inverter circuit I1 and I2 performs the logical inversion function to its input in generating the above corresponding outputs, the first and second pre-buffer logic output control signals 124 and 126. The first and second pre-buffer logic output control signals 124 and 126 are used to suitably drive transmitter logic 104 based on the information present in the at least one core logic output signal 118. In this manner, the first and second pre-buffer logic output control signal are a massaged form (that is, a translated form) of the at least one core logic output signal 118.
Transmitter logic 104 is coupled to the pre-buffer logic 106 and receives the first pre-buffer logic output signal 124 and the second pre-buffer logic 126. Transmitter logic 104 includes a plurality of 1X transistors. As used herein, transistors have two terminals and a gate, wherein the gate may be termed a third terminal. Transistors may be implemented in any suitable technology such as MOSFET technology. Transmitter logic 104 includes first pmos transistor P1, second pmos transistor P2, first nmos transistor N1 and second nmos transistor N2 coupled in a cascaded fashion: the first terminal of P1 is coupled to the first voltage source 108; the gate of P1 is coupled to receive the first pre-buffer logic output control signal 124; the second terminal of P1 is coupled to the first terminal of P2; the gate of P2 is coupled to the second voltage source 110 and to the gate of N1; the second terminal of P2 is coupled to the first terminal of N1; the second terminal of N1 is coupled to the first terminal of N2; the gate of N2 is coupled to the second pre-buffer logic output control signal 126; the second terminal of N2 is coupled to the ground. The output of transmitter logic 104, termed outgoing communication signals 128, is the voltage signal seen at the second terminal of P2 and the first terminal of N1. The first and second pre-buffer logic output control signals 124 and 126 control the transmitter logic 104 by controlling the gates of P1, P2, N1 and N2. Accordingly, when the core logic wishes to communicate information to, for example, another integrated circuit, the outgoing communication signal 128 matches the logic states of the transmission information associated with the at least one core logic output signal 118 but is at a higher voltage level. In this embodiment, the outgoing communication logic 128 has a logic one value of VDD_1 (i.e., 3.3 V).
FIG. 2 illustrates a block diagram of integrated circuit 200 similar to that of integrated circuit 100 of FIG. 1 with at least one core logic 202 and two different communication buffer logic rings: communication buffer logic ring_0 with power domain_0 204 and communication buffer logic ring_1 with power domain_1 206. Power domain_0 is associated with one voltage source (e.g., 3.3 V) while power domain_1 is associated with another voltage source (e.g., 5.0 V). The at least one core logic 202 may be associated with one or more corresponding voltage sources and may send core logic output signals to one or more communication buffer logic units 102. In this embodiment, the term “unit” is merely used to differentiate between each communication buffer logic 102. Each of the communication buffer logic rings 204 and 206 includes a plurality of communication buffer logic units 102 as illustrated in FIG. 1. Because each communication buffer logic unit 102 may communicate with one or more other integrated circuits, integrated circuit 200 is a versatile component of a electronic system requiring communication among a plurality of integrated circuits that require communication signals at either the voltage level associated with power domain_0 or the voltage level associated with power domain_1.
It is known that power domains can be characterized as having three operational modes. During a normal operation mode, all power supplies have sufficiently ramped up from 0 V to the voltage level at which they are designed to supply power. During ramp up operation mode, the power supplies are increased from 0 V to the voltage level at which they are designed to supply power. Conversely, during ramp down operation mode, the power supplies are decreased from the voltage level at which they are designed to supply power to 0 V.
Turning back to the prior art integrated circuit 100, during normal operation, the communication buffer logic 102 properly and accurately operates to deliver the correct outgoing communication signals 128 (and to receive and communicate to the core logic the correct incoming communication signals by way of the receiver logic, not shown). However, during ramp up operation mode and during ramp down operation mode, the voltage levels of the first voltage source 108 and the second voltage source 110 may cause the communication buffer logic 102 to act improperly and/or inaccurately thereby resulting in improper outgoing communication signals 128. The ramping voltage levels similarly and adversely affect the integrity of information contained within the incoming communication signals received by the receiver logic, not shown. This is complicated further because each of the voltage sources for the communication buffer logic 102 (and/or for the remainder of the integrated circuit 100, such as for example core logic) may be independently ramping up or down.
As a result of this sporadic, improper and inaccurate behavior of the communication buffer logic 102, the outgoing communication signals 128 transmitted by transmitter logic 104 may be improper and cause glitches or domino-effect errors for other integrated circuits that receive and rely on information contained therein. Although not specifically shown, if the communication buffer logic 102 includes receiving logic, the voltage ramping up and/or down of the first and second voltage sources 108 and 100 may further cause the core logic to receive inaccurate core logic input signals sent from other integrated circuits.
One prior art solution to the above referenced improper and inaccurate behavior of communication buffer logic 102 includes the use of external switches (e.g., weak pull-up transistors if there is a need to provide a logic one to another integrated circuit or weak pull down transistors if there is a need to provide a logic zero to another integrated circuit) that were placed alongside the trace or metal of a printed circuit board (PCB) communicating the outgoing communication signals 128 to another integrated circuit. The external switches are not only expensive, but cause additional signal integrity issues due to the difficulties of matching the impedance of the switch to the impedance of the trace. Because it is nearly impossible to properly match the impedance of the switch to that of the trace, the communication signal integrity was degraded due to reflection of the signals.
Accordingly, a need exists to correct the behavior of integrated circuits and specifically the communication buffer logic portions of integrated circuit during ramping periods such that communication signals may not cause other errors throughout the remainder of a system. A need further exists to provide such a solution while avoiding the use of external switches that cause further signal degradation.